In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g. search words) to the array and then performing a compare operation to identify one or more locations within the array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the compare operation, the identified location(s) containing equivalent data is typically encoded to provide an address at which the equivalent data is located. If multiple locations are identified is response to the compare operation, then priority encoding operations may be performed to identify a best or highest priority match. Such priority encoding operations frequently utilize the physical locations of multiple matches within the CAM array to identify a highest priority match.
CAM cells are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X), {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}.
CAMs are based on memory cells that have been modified by the addition of extra transistors to perform the comparison function. For writing and reading, each static CAM cell performs like a traditional SRAM cell, with differential bit lines to latch the desired value into the cell when writing, and sense amps to detect the stored value when reading. When writing, the appropriate word line of the CAM is selected, turning on the pass transistors that then force the cross-coupled transistors to the levels of the bit lines. When the word line is deselected, the cross-coupled transistors remain in the same state, thereby storing the desired value. For reading, the desired bit lines of the CAM are pre-charged to an intermediate voltage level and the desired word lines are selected. The bits lines are then forced to the levels stored by the cross-coupled transistors. A set of sense amps respond to the difference in the bit lines and output the stored value. For comparing, the matchline of the CAM is pre-charged to a high level, the bit lines are driven by the levels of the bits stored in a comparand register coupled to the CAM, but the word lines are not selected, so that the state of the cross-coupled transistors is not affected. The exclusive-NOR transistors then compare the internally stored bit of the cross-coupled transistors against the comparand bit, and if they do not agree, the matchline is pulled down, indicating a non-matching bit. All the bits in a stored entry are connected to the same matchline, so that if any bit in a word does not match with its corresponding comparand bit, that matchline is pulled down. A pulled down matchline therefore indicates a “miss” condition. Only the entries where the matchline stays HIGH are considered matches, indicating a “hit” condition.
The increasing size, density and complexity of CAMs make it extremely difficult to fabricate a CAM that is entirely free of defects. CAM defects can be reduced by improved fabrication methods and increased process controls, but there are practical limitations to implementing such methodologies. In the alternative, the yield of a CAM can be increased by circuit designs that can compensate for manufacturing defects. One such approach is the use of redundancy schemes. Both row and column redundancy schemes are well known in the art, and typically involve manufacturing a number of redundant memory cells in addition to the standard memory cells. The CAM is tested after fabrication and if defective standard cells are identified, they are replaced by the redundant cells.
Implementing redundancy schemes requires that the identified defective cells be disabled and then the replacement cells enabled. Conventional circuitry to enable replacement of a defective row with a redundant row in a CAM array involves fuse-programmable circuitry. Each row of a CAM array is typically connected to a word line and at least one matchline. Thus, to implement traditional row redundancy techniques in a CAM array it is necessary to shift the defective memory to a redundant row and also to turn off the associated hit circuit associated with the defective memory. A word line and the corresponding hit circuit are disabled when the fuse is blown in response to yield testing. The fuse line is associated with both the word line and the matchline.
Typically, the fuse lines for a CAM array are relatively long and susceptible to noise from adjacent lines in the array. If a sufficient level of noise is incident upon the matchline of a CAM array, the noise may propagate through the fuse line causing a previously disabled matchline to become enabled, thereby resulting in a possible hit error at the output of the CAM array.
It is known in the art to use a transmission gate or a pass gate on the fuse line to disable the hit circuit of a CAM array. The transmission gate provides XNOR logic along the fuse line. In such an embodiment, the transmission gate or pass gate is coupled along the fuse line and enabled, such that the input to the gate is passed to the output of the gate. As such, when a defective memory is identified, the fuse on the fuse line is blown to disable the word line and the transmission gate passes the result of the blown fuse to disable the corresponding hit circuit. However, transmission gates are nonrestoring gates, such that the noise at the input is coupled to the output. As such, if noise is incident upon the fuse line, that noise will be passed through the transmission gate. If the noise is sufficiently large, it may be sufficient to turn on the word line that was previously disabled and as such enable the corresponding hit circuit resulting in a hit error. Essentially, the pass gate in this configuration is equivalent to a resistor which allows noise to falsely turn on the word line. This situation is undesirable as it results in a defective CAM array.
In light of the above, a need exists in the art for an improved system and method for reducing the noise on a fuse line that is incident upon a hit circuit of a CAM array.